FPGA is an integrated circuit whose functionalities are designated by the users of the FPGA. The user programs the FPGA to perform the functions desired by the user. FPGA comprises logic cells, which perform the functions of the FPGA, and interconnection network between the logic cells. A prior art interconnection network is of a tree-based hierarchical architecture, in which interconnections of tree structure are used to make connections between logic cells of row-column layout. Heretofore, this interconnection network has been implemented as a quad-tree network, i.e. a switch box of upper level of hierarchy connecting to 4 logic cells or switch boxes of lower level of hierarchy, resulting in a circuit with number of logic cells amounting to power of 4. For example, FPGA would have 1024, 4096, and 16384 logic cells with respect to level number of hierarchy of 5, 6 and 7. Apparently, there exist some applications, which may need for example 1500 logic cells but have to be implemented in FPGA with 4096 logic cells. That is to say, only a small part of logic cells could be utilized in this circuit. Currently, Integrated Circuits have vast applications in various fields. In certain circumstances, the number of logic cells as demanded is not always a power of 4 or close to. Building such an IC by quad-tree interconnect network would inevitably lead to non-effective use of chip area.
Furthermore, the integrated circuit with quad-tree hierarchical interconnection architecture will inevitably have an approximately square layout. In case of a so-called System-on-a-Chip (SOC), which usually has a square layout and contains several integrated circuits, it has been proved difficult to place such integrated circuits on the chip.